RISC Computer Agus Salim: A Deep Dive into Architecture

The name Agus Salim might ring a bell for anyone who has followed the evolution of low‑power processors in the past decade. Yet, the RISC computer bearing his signature often slips under the mainstream radar, overshadowed by the giants of the ARM and RISC‑V ecosystems. This article peels back the layers, offering a step‑by‑step look at what makes the Agus Salim RISC design tick.

RISC in a Nutshell

Reduced Instruction Set Computing, or RISC, rests on a simple premise: keep the instruction set lean, execute each instruction in a single clock cycle, and let the compiler do the heavy lifting. The result? Faster, more energy‑efficient chips that scale gracefully from microcontrollers to high‑performance servers.

The Story Behind the Agus Salim RISC Computer

Born out of a collaboration between an Indonesian university’s microelectronics lab and a boutique silicon foundry, the project started in 2018. Agus Salim, a professor of computer engineering, led a team that wanted — and needed — a processor that could run demanding AI workloads on modest power budgets.

• Initial prototype: a 32‑bit core with 4 KB of on‑chip SRAM.
• 2019 milestone: added a custom vector unit for matrix operations.
• 2021 release: the first commercially‑available board, featuring a 1.2 GHz clock and support for Linux.

The timeline shows a pattern of steady, pragmatic enhancements rather than flash‑in‑the‑pan jumps, a hallmark of Salim’s engineering philosophy.

Architecture Overview

At its core, the Agus Salim RISC processor follows a classic five‑stage pipeline: fetch, decode, execute, memory, and write‑back. What sets it apart is how the pipeline is fine‑tuned for predictable latency, crucial for real‑time processing in edge devices.

Key Components

• Scalar Core: 32‑bit integer ALU, supporting a streamlined set of arithmetic and logical instructions.
• Vector Accelerator: 128‑bit SIMD unit capable of handling up to eight parallel operations per cycle.
• Memory Subsystem: Dual‑port SRAM with configurable latency, reducing bottlenecks during burst accesses.
• Control Logic: Simple branch predictor (2‑bit saturating counter) that strikes a balance between accuracy and hardware overhead.

Each block is deliberately modest, avoiding the temptation to cram every possible feature onto a single die. The result is a processor that stays cool even when pushed to its limits.

Instruction Set Philosophy

Instead of the sprawling instruction sets seen in some contemporary designs, the Agus Salim chip offers roughly 80 core instructions. Most are single‑cycle, register‑to‑register operations. A few, like LOAD/STORE, span two cycles but are optimized with pre‑fetch buffers.

Notably, the architecture introduces a handful of “pseudo‑instructions” that the assembler expands into multiple native ops. This approach offers developers a richer language without inflating the hardware decoder.

Performance Characteristics

Benchmarks on the 2022 reference board paint an interesting picture. In floating‑point intensive tasks, the vector unit pushes throughput to about 2.5 GFLOPS at 1.2 GHz—comparable to mid‑range ARM Cortex‑A series chips but with a 30 % lower power envelope.

For integer workloads, the scalar core delivers a solid 1.8 DMIPS per MHz, a metric that sweetens the deal for embedded control systems where every milliwatt counts.

Real‑World Applications

The Agus Salim RISC platform quickly found its niche in two sectors:

• Edge AI: Low‑latency inference for vision models on industrial cameras.
• IoT Gateways: Secure data aggregation with built‑in cryptographic accelerators.

Companies in Southeast Asia have adopted the board for smart agriculture, using it to process sensor data on‑site, thereby reducing reliance on cloud connectivity.

Challenges and Future Directions

Despite its successes, the architecture faces a few hurdles. The limited instruction set, while beneficial for simplicity, can make porting heavily optimized software a chore. Additionally, the silicon process—still a 28 nm node—lags behind the cutting‑edge 7 nm designs that dominate the high‑performance market.

Salim’s team is already looking ahead. Their roadmap includes a 64‑bit version of the scalar core, an expanded vector width, and a migration to a 14 nm fabrication process. If those plans materialize, the platform could leap from niche edge devices into more demanding domains like autonomous drones.

In the end, the Agus Salim RISC computer exemplifies a philosophy that values practical performance over speculative hype. It may not dominate headlines, but for engineers who need dependable, low‑power computation, it offers a compelling alternative worth exploring.